This paper proposes a new ultra-compact strip metal-Insulator-metal (MIM) plasmonic waveguide on a Silicon-on-Insulator (SOI) platform. The waveguide structure can efficiently propagate surface plasmon polaritons (SPPs) within a thin low-index SiO2 layer at an optical wavelength window of 1550 nm. The main parameters of effective refractive index, propagation length, confinement factor, and effective mode area were determined for the proposed waveguide with different waveguide widths. The simulation results were comparable with the in-plane MIM plasmonic waveguide. The proposed layer stack could be monolithically integrated with conventional and hybrid plasmonic SOI-based devices and has the potential of focusing light to nanoscale dimensions.

IIn this paper, we proposed a short channel Silicon on Insulator Metal-oxide Semiconductor-Field-Effect-Transistor (SOI-MOSFET), in which a thin layer of n+-type doping has been expanded from top of its entire source region into the channel and also a proportionally heavily p-type retrograde doping has been implanted in its channel, close to the source region. Due to source doping expansion in the channel, we call this structure as Source Expanded Doping Silicon on Insulator (SED-SOI) structure. This expanded n+ doping increases the carrier concentration in the source, which can be injected into the channel. Moreover, it increases the amount of carriers, which can be controlled more effectively by the gate electrode. These two advantages enhance both ON state current and transconductance in the device more than 1.9 mA and 5 mS, respectively. Engineered p-type retrograde doping profile causes impurity scattering and this reduces electron mobility in the depth of the device channel, which in turn OFF current decreases down to 0.2 nA. An immense comparison among our proposed device and a conventional structure (C-SOI) shows that it has better performance in terms of Ion/Ioff ratio (>9.5×105), subthreshold swing (75 mV/dec), leakage current, breakdown voltage, hot carrier injection and DIBL. Our analysis demonstrate that SED-SOI transistor can be an excellent candidate for both low power and high performance applications.

Silicon on Insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from high subthreshold slope (SS) as well as high leakage current. As a result, the SOI-JLFET device has limitation for high speed and low power applications. For the first time in this study, use of the auxiliary gate in the drain region of the SOI-JLFET has been proposed to improve the both SS and leakage current parameters. The proposed structure is called "SOI-JLFET Aug". The optimal selection for the auxiliary gate work function and its length, has improved the both SS and ION/IOFF ratio parameters, as compared to Regular SOI-JLFET. Simulation results show that, SOI-JLFET Aug with 20nm channel length exhibits the SS~71mV/dec and ION/IOFF~1013. SS and ON-state to OFF-state current (ION/IOFF) ratio of SOI-JLFET Aug are improved by 14% and three orders of magnitudes, respectively, as compared to the Regular SOI-JLFET. The SOI-JLEFT Aug could be good candidate for digital applications.

In this work, a novel Silicon on Insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a Silicon region has embedded in the buried oxide. In order to reduce the device leakage current and controlling the threshold voltage, a p-type retrograde doping is introduced into channel region. Since the air has the least permittivity among materials, it can be utilized to decrease the device parasitic capacitances. Based on this, an air gap is embedded in the buried oxide near the Silicon to improve RF performance of the device. Because the source and drain electrodes are embedded in and over the Silicon film in the source and drain regions, we called this structure EEIOS-SOI MOSFET. “ EEIOS” stands for “ Embedded Electrodes In and Over the Silicon film” . During this work, EEIOS-SOI MOSFET is compared with a conventional SOI MOSFET and another SOI MOSFET with just Embedded Electrodes In the Silicon Film (EEISSOI). EEIS-SOI presents better electrical figure of merits including lower subthreshold slope and lower leakage current in simulations. An immense investigation among these devices shows that EEIOS-SOI MOSFET has better transconductance, lower gate injection leakage current and lower temperature related to DC parameters and higher cut off frequency, gain bandwidth product and unilateral power gain related to AC figures of merits compared to its counterparts.

In this paper, for the first time, an analytical equation for threshold voltage computations in Silicon-on-diamond MOSFET with an additional insulation layer is presented; In this structure, the first insulating layer is diamond which covered the Silicon substrate and second insulating layer is SiO2 which is on the diamond and it is limited to the source and drain on both sides. Analytical solution was used to determine the threshold voltage by computations of capacitors in buried Insulators. Simulation and Analytical results of threshold voltage in Silicon-on-diamond and Silicon-on-Insulator with the same dimensions and channel length were compared. Theeffect of device parameters like gate oxide thickness, Silicon body thickness, length and thickness of oxide on threshold voltage of the Silicon-on-diamond MOSFET were investigated and the analytical results were compared against device simulation findings.

In this paper, we have investigated the transport properties of the Dirac fermions on a topological Insulator surface in the presence of external electric and magnetic fields. For this reason, firstly we obtain the eigen energies (or eigenvalues) by using the Dirac Hamiltonian of the system for transmitted electrons via the surface and the Lorentz transformations. The conductance of the system is calculated by Landauer equation. Also, the effects of electric and magnetic fields are investigated on the conductance and Fano factor effect. The application of the present results may be useful in designing devices based on molecular electronics in nanoscale.

In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried oxide thickness has been reduced into the half and a part of it has been replaced by a buffer layer. Increase in the thermal conduction and making an extra depletion layer in the buffer layer/channel region interface are led to improvement of the electrical performance in the terms of DC and AC. In the proposed method, which is based on the energy band modification, the parameters such as IOFF, ION/IOFF, subthreshold swing, lattice temperature, voltage gain, transconductance, parasitic capacitances, power gains, cut-off frequency, maximum oscillation frequency and minimum noise figure have been improved. Also, a designing consideration for the role of buffer layer on the proposed device has been performed. Comparing structures under the study simulated by the SILVACO showed the electrical performance superiority for the proposed device.

In this article, a novel concept is introduced to improve the Radio Frequency (RF) linearity of Partially-Depleted (PD) Silicon-On-Insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown.3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz Low Noise Amplifier (LNA) is analyzed. Mixed mode device circuit analysis is carried out to simultaneously solve device carrier transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third Harmonic Distortion (HD3) and Total Harmonic Distortion (THD) are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.